The present invention relates in general to the use of on-chip test-only circuitry to test the functional circuitry of an integrated circuit (IC). More specifically, the present invention relates to operating methodologies, fabrication methodologies, and resulting structures that determine proper operation of on-chip test-only circuitry across a wide range of test conditions, do not limit the speed at which the functional circuitry operates, and minimize current draw of the test-only circuitry during normal operation of the functional circuitry.
It is known to test the functional circuitry of ICs during fabrication. A known method of testing an IC in-use is to provide on-chip test circuitry known generally as built-in self-test (BIST) circuitry or engines. In a basic configuration, a BIST circuit/engine applies an input test pattern to a circuit-under-test (CUT), and then compares the CUT output response to known-good circuit output responses. If the CUT output response is within an acceptable range of known-good circuit output responses, the BIST circuit indicates that the CUT passed, and the CUT is determined to be fault-free. If the CUT output response is outside an acceptable range of known-good circuit output responses, the BIST circuit indicates that the CUT failed, and the CUT is determined to be faulty.